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38 GNU make
If you cannot be sure of the precise contents of the directories you are using, you may
not be sure which other irrelevant files might lead make to use the wrong implicit rule.
The choice might depend on the order in which the implicit rule search is done. With
static pattern rules, there is no uncertainty: each rule applies to precisely the targets
specified.
4.12 Double-Colon Rules
Double-colon rules are explicit rules written with :: instead of : after the target names.
They are handled differently from ordinary rules when the same target appears in more
than one rule. Pattern rules with double-colons have an entirely different meaning (see
Section 10.5.5 [Match-Anything Rules], page 123).
When a target appears in multiple rules, all the rules must be the same type: all ordinary,
or all double-colon. If they are double-colon, each of them is independent of the others.
Each double-colon rule’s recipe is executed if the target is older than any prerequisites of
that rule. If there are no prerequisites for that rule, its recipe is always executed (even if
the target already exists). This can result in executing none, any, or all of the double-colon
rules.
Double-colon rules with the same target are in fact completely separate from one another.
Each double-colon rule is processed individually, just as rules with different targets are
processed.
The double-colon rules for a target are executed in the order they appear in the makefile.
However, the cases where double-colon rules really make sense are those where the order of
executing the recipes would not matter.
Double-colon rules are somewhat obscure and not often very useful; they provide a
mechanism for cases in which the method used to update a target differs depending on
which prerequisite files caused the update, and such cases are rare.
Each double-colon rule should specify a recipe; if it does not, an implicit rule will be
used if one applies. See Chapter 10 [Using Implicit Rules], page 111.
4.13 Generating Prerequisites Automatically
In the makefile for a program, many of the rules you need to write often say only that
some object file depends on some header file. For example, if main.c uses defs.h via an
#include, you would write:
main.o: defs.h
You need this rule so that make knows that it must remake main.o whenever defs.h
changes. You can see that for a large program you would have to write dozens of such rules
in your makefile. And, you must always be very careful to update the makefile every time
you add or remove an #include.
To avoid this hassle, most modern C compilers can write these rules for you, by looking
at the #include lines in the source files. Usually this is done with the -M option to the
compiler. For example, the command:
cc -M main.c
generates the output:
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